S1C33L19 cmos 32-bit application specific controller 32-bit risc cpu-core optimized for soc (epson s1c33 pe) dual amba bus system for cpu and lcdc built-in pll (multiplication rate: 1 to 16) advanced cpu instruction queue buffer built-in 8kb ram + built-in vram/ram (12kb) sdram controller with burst control generic dma controller (hsdma/idma) 4-ch. pwm control timer/counter supports several interfaces sio with fifo (irda1.0, iso7816-3), spi, i2s and usb 5-ch. adc for analog input built-in lcd controller with 12kb ivram supports up to qvga (320 240) display in 1 bpp mode (black and white) by single chip supports vga (640 480) and 64k color built-in jpeg decoder/encoder built-in usb controller (device) full speed (12mbps) supports i 2 s interface (in/out) nand flash interface ? descriptions the S1C33L19 is a cost-effective, high-performance 32-bi t risc controller designed specifically for graphic display applications. it incorporates lcd display functions and jpeg image processing for electronic devices requiring lcd display of images, such as photo viewers and other compact image display units, home intercoms and other home electronic devices, as well as operating panels incorporated into various office equipment. the jpeg image processing function uses an internal hardware accelerator for high-load jpeg processing to achieve faster processing than software proce ssing alone. it is provided as an easy-to-use jpeg decoder/encoder api with complex controls handled interna lly, allowing easy interfacing with applications for easy, high-speed enlargement and compression of jpeg image data, including photographs, improved application display capabilities, and smaller data sizes. peripheral circuits and pin layout are completely fo rward-compatible with the s1c33l17, enabling use with applications that rely on adc f unctions and a wide range of serial interfaces, including numerous general-purpose input/output ports , powerful pwm timer/counter, and usb-fs device controller. the S1C33L19 consists of a 32-bit risc cpu core, jpeg decoder/encoder, general-purpose dma controller, usb-fs device controller, pwm control timer/counter, several interfaces (irda1.0, sio including iso7816-3 protocol, spi and i2s), adc, ram, general-purpose ram shared ivram, rtc, and nand flash interface implemented by epson soc design technology using a 0.18 m fine-pattern cmos process. ? features technology ? 0.18 m al-4-layers mixed analog low power cmos process technology cpu ? epson original c33 pe 32-bit risc cpu-core with amba bus optimized for soc ? max. 66 mhz operation ? internal 2-stage pipeline and 4 instruction queues ? instruction set: 128 instructi ons (16-bit fixed length) ? basic instructions are compatible with the s1c33 32-bit risc cores. ? dual amba bus system for cpu and lcdc
S1C33L19 2 seiko epson corporation internal memories ? 8k-byte ram ? 12k-byte ivram (used as general-purpose ram or vram) ? 2k-byte dst ram (used as general-purpose ram or idma descriptor table ram can be used to store multiplicand when the build in mac and api is used.) oscillator circuit / pll osc3 oscillator circuit ? crystal oscillation: 5 mhz min. to 48 mhz max. ? ceramic oscillation: 5 mhz min. to 48 mhz max. ? external clock input: 5 mhz min. to 48 mhz max. ? a 48 mhz clock source with 0.25% of accuracy should be connected for us ing the usb function. ? before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. pll ? pll input frequency: 5 mhz min. to 50 mhz ma x. (osc3 1, 1/2, 1 /3 ... 1/9, 1/10) ? pll output frequency: 20 mhz min. to 90 mhz max. ? multiplication rate: 1 , 2, 3, ... 15, 16 osc1 oscillator circuit ? crystal oscillation: 32.768 khz typ. ? external clock input: 32.768 khz typ. hardware accelerator module jpeg decoder/encoder ? high-speed processing using internal hardware accelerator ? jpeg-baseline (itu-t t.82 and jis x4081 compliant) ? supported markers: soi, dqt, dht, sof0, dri, sos, eoi ? jpeg image formats: yuv444, yuv422, yuv420, yuv411, grayscale ? bitmap formats: rgb 24/16/8-bit, grayscale 4/2/1-bit ? high-speed reduction function: 1/1, 1/2, 1/4, 1/8 shrink mode ? split decoding/encoding is possible to reduce memory usage ? supported image data size: unlimited (dependent on available memory size) ? api list jpeg header analysis (jpeganalyze) jjpeg decoding (jpegdecode) jpeg encoding (jpegencode) ? decoding time: vga (640x480): 1012 [msec] (typ.) qvga (320x240): 287 [msec] (typ.) qqvga (160x120): 86 [msec] (typ.) * operating at 66 mhz, vram: color 16-bit, q value = 75, yuv420 format ? encoding time: vga (640x480): 1572 [msec] (typ.) qvga (320x240): 415 [msec] (typ.) qqvga (160x120): 116 [msec] (typ.) * operating at 66 mhz, vram: color 16-bit hardware calculation module allows high-speed processing using internal hardware accelerator. ? 4/8/16-element product- sum calculation (mac) ? 2/3/4-order matrix calculation (matrix) ? 2/3-order affine conversion (affine) ? butterfly calculation (butterfly) supports the following calculati on modes as numerical equations. ? signed/unsigned 32-bit integer ? q13/14 16-bit fixed decimal point value (float16_q13/float16_q14) supports saturation processing to prevent numerical ov erflows. (16-bit fixed decimal point value only) high speed bus (hb) modules sramc (sram controller)
S1C33L19 seiko epson corporation 3 ? 25-bit address lines and 8/16-bit selectable data bus ? up to a 512m-byte (a[24:0]) address spac e is provided for each chip enable signal. ? max. 8 chip enable signals are available to connect external devices. ? programmable bus wait cycle (0 to 7 cycles) ? supports external wait signals. ? 4gb physical address space is available. - the physical address space is divided into 23 areas: area 0 to area 22. - areas 0 to 4 and area 6 are system reserved. ? supports only little-endian access to each area. ? memory mapped i/o ? supports both a0 and bs (bus strobe) access type external devices. ? sram, rom, and flash rom direct access interfaces are built in. sdramc (sdram controller with sdram app and ahb local bus arbiter) ? supports sdram direct interface. ? supports only sdram devices with 16-bit data bus. minimum configuration: 16m bits (2mb), 16-bit sdram 1 maximum configuration: 512m bits (64mb), 16-bit sdram 1 ? cas latency: 1, 2 or 3 programmable ? supports burst and single read/write. ? supports dqm (byte write) function. ? supports max. 4 sdram banks and bank active mode. ? incorporates a 12-bit auto-refresh counter. ? intelligent self-refresh func tion for low power operation ? 2-stage 32-bit data buffer and 8-stage 16-bi t 2-slot instruction buffer built-in ? supports up to 90 mhz sdram clock. - when the cpu clock is 48 mhz, the sdram clock can be set to 48 mhz. - when the cpu clock is 45 mhz, the sdram clock can be set to 90 mhz using the pll. ? arbitrates ownership of the external bus between the cpu, dmac, lcdc and sramc. dmac (direct memory access controller) ? 4-ch. high speed hardware dma ? 128-ch. intelligent dma (variable data transfe r controller) with specific control table ivramarb (internal video ram arbiter) ? contains a 12kb sram (3,072 words 16 bits 2). ? arbitrates accesses from the lcdc and cpu. ? allows the cpu and lcdc to access ivram in minimum 2 cycles by 32-bit access. ? supports uma (unified memory access) for display. ? ivram is configurable as a 12kb general -purpose ram in area 0 using a control register if it is not used as a video ram. peripheral bus (sapb) modules tcu (timer/counter unit with pwm outputs) ? 4-ch. 16-bit timer/counter ? supports pwm outputs with da16 (digital d/a) mode. ? contains a prescaler, which can divide the peripheral clock by 1 to 4,096, to generate t he operating clock for each channel. ? possible to invoke dma transfer. wdt (watchdog timer) ? 30-bit watchdog timer to generate an nmi interrupt ? the watchdog timer overflow cycle (nmi interrupt cycle) is programmable. ? the watchdog timer overflow signal can be output outside the ic. adc (a/d converter) ? 5-ch. 10-bit a/d converter ? upper/lower limit interrupt is available. ? each adc channel includes a data buffer. ? contains a prescaler, which can divide the peripheral clock by 2 to 256, to generate the operating clock for adc. itc (interrupt controller)
S1C33L19 4 seiko epson corporation ? possible to invoke dma transfer ? dma controller interrupt: 5 types ? input interrupt: 18 types ? tcu interrupt: 8 types ? efsio interrupt: 9 types ? adc interrupt: 2 types ? rtc interrupt: 1 type ? spi interrupt: 3 types ? usb interrupt: 2 types ? i 2 s interrupt: 2 types ? lcdc interrupt: 1 type gpio (general-purpose i/o ports) ? max. 82 ports in the tqfp24-144pin model. * the S1C33L19 gpio ports are shared with other peripheral function pins (efsio, pwm etc.). therefore, the number of gpio ports depends on the peripheral functions used. therefore, the number of gpio ports depends on the peripheral functions used. ? supports usb2.0 full speed (12m bps) mode. ? supports auto negotiation function. ? supports control, bulk, isoc hronous and interrupt transfers. ? supports 4 general-purpose end poi nts and end point 0 (control). ? embedded 1k-byte programmable fifo ? supports 8-bit local bus dma port. ? possible to invoke dma transfer. ? supports async. dma transfer. ? supports dma slave mode. ? fixed 48 mhz clock for usb-fs. ? supports snooze mode. rtc (real time clock) ? contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). ? bcd data can be read from and written to both counters. ? capable of controlling the star ting and stopping of time clocks. ? 24-hour or 12-hour mode can be selected. ? a 30-second correction function can be implemented in software. ? periodic interrupts are possible. card (serial input/output with direction control) ? provides smartmedia i/f signals (#smre, #smwe). ? provides 8-bit nand flash i/f signals. ? hardware reed-solomon codec for eit her mlc or slc nand error detection. ? supports nand flash booting function. efsio (extended serial interface with fifo buffer) ? 2-ch. clock sync./async. serial interface ? contains fifo data buffers (4 receive data buffer and 2 transmit data buffer are available for each channel). ? supports irda1.0 interface. ? contains a baud-rate generator (12-bit programmable timer). ? supports iso7816 mode (ch.1 only). - alternative msb or lsb - memory card interface compatible with iso7816-3 t=0 & t=1 protocol - programmable baud-rate and guard-time generation - iso7816 acknowledge and automat ically repeat transmission ? possible to invoke dma transfer. uart ? async. only serial interface (uart) with 1 byte transmit data buffer and 2 bytes receive data buffer (ch.2). ? built-in programmable 12-bit timer is available for baud-rate generators. ? possible to invoke dma transfer. spi (serial peripheral interface) ? 1 ch. spi that operates in either master or slave mode
S1C33L19 seiko epson corporation 5 ? supports 1- to 32-bit data transfer. ? data transfer timing (clock phase and polarity va riations) is selectable from among 4 types. ? a 1 to 65,536 clocks of delay can be inserted between transfers. ? generates transmit data regi ster empty and receive data register full interrupts. ? support both mmc & sd card capabilities. ? possible to invoke dma transfer. ? max. bit rate in master mode is mclk/2. egpio (extended gpio) ? max. 17 configurable gpio ports are available in addi tion to the standard gpio ports. in die form, max. 91 ports are available. * the egpio ports are shared with other peripheral function pins. therefore, the number of egpio ports depends on the peripheral functions used. ? most ports have a pull-up resistor that c an be enabled/disabled with the control register. ? possible to drive the ports low. cmu (extended clock management unit) ? controls clock supply to each peripheral module (static). ? manages reset and nmi inputs. ? switches the system clock source (mclk, sdram_clk, or rtc_clk). ? controls the mclk and rtc_clk oscillator circuits. ? turns on/off and controls frequency mu ltiplication rate of the pll. ? controls clocks according to the standby mode (sleep and halt). ? controls divide ratios of the lcdc clock. ? manages the external bus clock. misc (misc. setting register) ? usb/rtc wait conf iguration registers ? debug port function select register ? boot mode confi guration register i 2 s (inter-ic sound bus interface) ? supports universal audio i2s bus interface. ? support 16 bit or 24 bit data format for both input channel and output channel. ? generate the bit clock, word-sel ect signal, data and master clock. ? master clock can be generated inter nally, or input from external. ? generate 2 i 2 s interrupt signals. ? generate 4 i 2 s hsdma trigger signals. lcdc (stn/tft lcd controller with amba bus) vram: ? built-in a 12kb ram usable as a display buffe r or general-purpose ram (register selectable) ? supports the uma method allowing lcdc to access s dram (external vram) or ivram (internal vram). ? the external vram map (sdram) is configurable. ? the sub-window area can be located in ivram or exte rnal vram regardless of whether it contains the main window area or not. display support: ? 4- or 8-bit monochrome lcd interface ? 4- or 8-bit color lcd interface ? single-panel, single-drive passive displays ? 12 or 16-bit generic hr-tft interface - 320 240-dot sharp hr-tft panel, sii liquid tft panel, or some other tft panels ? typical resolutions - 320 240 (8-bpp mode, external vram is required) bpp = bits per pixel - 320 240 (1-bpp mode) * note that the panel width must be a multiple of 16 bits per pixel. display modes: ? due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a monochrome passive lcd panel is used. - two-shade display in 1-bpp mode - four-shade display in 2-bpp mode - 16-shade display in 4-bpp mode
S1C33L19 6 seiko epson corporation ? a maximum of 64k colors can be simultaneously displayed on a color passive lcd panel. - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode - 64k-color display in 16-bpp mode ? a maximum of 65536 colors can be simultaneously displayed on a tft panel. - two-color display in 1-bpp mode - four-color display in 2-bpp mode - 16-color display in 4-bpp mode - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode - 64k-color display in 16-bpp mode ? a look-up table, which consists of 6 bi ts 16 entries 3 colors, is provided. - in monochrome 1/2/4-bpp or co lor 8/12-bpp mode, the look-up t able can be used or bypassed. - in color 1/2/4/16-bpp mode, the look- up table cannot be used (must be bypassed). display features: ? picture-in-picture plus (pip+) picture-in-picture plus enables a secondary window (or sub-window) within the main display window. the sub-window may be positioned anywhere within the main window and is controlled through registers. the sub-window retains the same color depth as the main window. the speed of generating a sub-window by hardware is faster than software. by using this pip+ function, it can greatly speed the gui performance and cpu can have more performance to assign other processing. (e.g. voice etc.) ? 12 or 16-bit generic hr-tft interface the 12 or 16-bit generic hr-tft interface c an support 320 240 sharp hr-tft panel, sii tft panel or some other tft panels. because the timing of fpfram, fpline, fpshift and tft_ctl0?3 are not fixed for tft panels, they can be controlled by register setting. by different register settings, you can get your specified tft i/f signal timing. ? clock source the lcdc clock can be internally divided 48 mhz by 1 to 16. the clock division register is located in cmu part. operating voltage ? vdd (core): 1.70 to 1.90 v (typ. 1.8 v) when a ceramic resonator is used ? vdd (core): 1.65 to 1.95 v (typ. 1.8 v) when a crystal is used or an external clock is input ? plvdd: 1.65 to 1.95 v (typ. 1.8 v) ? vddh (i/o): 2.70 to 3.60 v when the usb is not used (5-v tolerant i/o not supported) ? vddh (i/o): 3.00 to 3.60 v (typ. 3.3 v) when t he usb is used (5-v tolerant i/o not supported) operating frequency ? cpu: 66 mhz max. ? usb: 48 mhz fixed. ? sdramc: 90 mhz max. ? lcdc: 66 mhz max. ? other peripheral circuits: 66 mhz max. operating temperatures ? -40 to 85c (0 to 70c when a ceramic resonator is used) current consumption ? during sleep: 0.3 a typ. (operation clock = 48 mhz) ? during halt: 3.2 ma typ. (operation clock = 48 mhz) ? during execution: core 22.0 ma typ. (operation clock = 48 mhz) sramc 3.6 ma typ. (operation clock = 48 mh z, idle state with the clock supplied) sdramc 5.6 ma typ. (operation clock = 48 mh z, idle state with the clock supplied) dma 4.1 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) lcdc 5.6 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) usb 10.0 ma typ. (operation clock = 48 mhz, idle state with the clock supplied)
S1C33L19 seiko epson corporation 7 adc 260.0 a typ. (idle state when adc is enabled) jpeg 25.0 ma typ. (with 48 mhz operati ng clock, jpeg decoder /encoder operation) * by controlling the cpu clock through the clock-g ear (cmu), current cons umption can be reduced. shipping form ? package: tqfp24-144pin (16 mm 16 mm 1.0 mm and 0.4 mm pin pitch) pfbga-180pin (12 mm 12 mm 1.2 mm and 0.8 mm ball pitch) ? die form: 168 pads with pad pitch 90 m
S1C33L19 8 ? block diagram area 0 a0ram (ivram) (12kb) a0ram (8kb) pe_e07_cpu location of ivram can be selected by a register. (used as a ram) (used as a vram) area 3 ivram (12kb) dst ram (2kb) ivram arbiter cpu_ahb jpeg decoder jpeg encoder calculation module h/w accelerator s1c33pe_amba: master 1 a18m pll dma gp sramc (sapb bridge) dma gp registers hsdma idma dma gp: master 2 a6dec external memory i/f lcdc_ahb lcdc lcdc_amba: master iqb dqb dqb sdapp1 sdapp2 arbiter sdramc_ip mux area 10 gate rom (4 words) a6_x32 devices area 6 cmu sdramc registers i 2 s lcdc registers rtc spi sramc registers dma gp registers tcu16 (4 ch.) wdt adc a6_x16 devices a6_x8 devices efsio (2ch.) egpio itc card i/f misc registers usb uart (1ch.) gpio << << < x32 x32 x32 x32 x32 x32 x32 x16 x16 x16 area 0 a0ram (ivram) (12kb) a0ram (8kb) pe_e07_cpu location of ivram can be selected by a register. (used as a ram) (used as a vram) area 3 ivram (12kb) dst ram (2kb) ivram arbiter cpu_ahb jpeg decoder jpeg encoder calculation module h/w accelerator s1c33pe_amba: master 1 a18m pll dma gp sramc (sapb bridge) dma gp registers hsdma idma dma gp: master 2 a6dec external memory i/f lcdc_ahb lcdc lcdc_amba: master iqb dqb dqb sdapp1 sdapp2 arbiter sdramc_ip mux area 10 gate rom (4 words) a6_x32 devices area 6 cmu sdramc registers i 2 s lcdc registers rtc spi sramc registers dma gp registers tcu16 (4 ch.) wdt adc a6_x16 devices a6_x8 devices efsio (2ch.) egpio itc card i/f misc registers usb uart (1ch.) gpio << << < x32 x32 x32 x32 x32 x32 x32 x16 x16 x16 semiconductor operations division seiko epson corporation ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ?seiko epson corporation 2009, all rights reserved. http://www.epson.jp/device/semicon_e/ ? epson semiconductor website document code: 411549301 first issue mar, 2009 revised dec , 2009
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